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Guided learning journeys that build knowledge step by step.
category · Learning · slug · learning · 7813 Paths
7813 Paths · page 430 / 782
This graduate-level path explores the theoretical underpinnings of advanced computer architectures, contrasting von Neumann and non-von Neumann models, and delving into dataflow and systolic array paradigms. Learners will analyze execution models, concurrency, and design trade-offs, preparing them for research in unconventional computing.
This learning path explores the architectural principles and implementations of Single Instruction, Multiple Data (SIMD) processing. It covers the fundamentals of data-level parallelism, vector processing, SIMD extensions in modern processors, and the implications of vector length and operations. Designed for university students in high-performance computing, it progresses from foundational concepts to advanced architectural considerations.
This learning path provides system architects with a deep understanding of modern storage and I/O technologies, from foundational I/O systems to advanced NVMe, SSD controllers, storage arrays, and Fibre Channel. It emphasizes performance analysis and design considerations for high-performance storage systems.
This learning path systematically builds from multiprocessor and cache fundamentals to advanced coherence protocols and consistency models. It covers MESI and MOESI protocols, sequential and release consistency, and the interplay between coherence and consistency, culminating in the ability to analyze and reason about memory consistency challenges in modern multiprocessor systems.
This path covers advanced branch prediction and speculation techniques in modern processors, starting from the fundamentals of control hazards and pipelining, through static and dynamic prediction, to speculative execution and recovery mechanisms. It is designed for university students in high-performance computing who want a systematic understanding of control flow optimization.
This learning path guides advanced computer architecture students through the principles and design of processors that execute multiple instructions per cycle. Starting with pipelining fundamentals, it progresses through superscalar issue, dynamic scheduling, register renaming, and memory disambiguation, and concludes with VLIW concepts and a comparison of design approaches.
This learning path introduces the key concepts of parallel computer architectures, starting with the basics of cache memory and pipelining, then progressing through multiprocessor organizations, cache coherence protocols, memory consistency models, and synchronization mechanisms. It is designed for university students with a background in computer organization who want to systematically understand the hardware foundations of parallel systems.
A structured path to design and analyze processor datapaths. It begins with foundational digital logic and ISA concepts, then builds the single-cycle datapath, and finally extends to multi-cycle control and timing.
This learning path equips students and professionals with the knowledge and skills to measure and analyze computer performance. It covers fundamental metrics, performance equations, benchmarking, and the impact of parallelism through Amdahl's law, providing a solid foundation for performance analysis in computer architecture.
A systematic path through computer I/O, from interfaces and control methods to storage technologies and RAID. Builds on processor and memory fundamentals to enable informed system design decisions.